ADZS-21371-EZLITE【PDF 8/56 页】KIT EVAL EZLITE ADZS-21371

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ADSP-21371 / ADSP-21375

SHARC processor are 48 bits wide, instruction throughput

when executing code from external SDRAM memory is 2

instructions every 3 SDCLK (peripheral) clock cycles over a 32-

bit wide external port, and 2 instructions every 6 SDCLK clock

cycles over a 16-bit external port. Non SDRAM external mem-

ory address space is shown in Table 6 .

Table 6. External Memory for Non SDRAM Addresses

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the processor’s DAI pins

(DAI_P1 to DAI_P20).

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in Words

14M

16M

16M

16M

Address Range

0x0020 0000–0x00FF FFFF

0x0400 0000–0x04FF FFFF

0x0800 0000–0x08FF FFFF

0x0C00 0000–0x0CFF FFFF

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1 .

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 32-bit data bus, is 177M bytes/s for the AMI and 532M

bytes/s for SDRAM.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit or 16-bit wide buses for ease of interfac-

ing to a range of memories and I/O devices tailored either to

high performance or to low cost and power.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

In the ADSP-21371, the DAI includes eight serial ports, four

precision clock generators (PCG), and an input data port (IDP).

For the ADSP-21375, the DAI includes four serial ports, four

precision clock generators (PCG) and an input data port (IDP).

The IDP provides an additional input path to the core of the

processor, configurable as either eight channels of I 2 S serial

data, or a single 20-bit wide synchronous parallel data acquisi-

tion port. Each data channel has its own DMA channel that is

independent from the processor’s serial ports.

Serial Ports

The processors feature eight synchronous serial ports on the

ADSP-21371 and four on the ADSP-21375. The SPORTs pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

For the ADSP-21371, serial ports are enabled via 16 program-

mable pins and simultaneous receive or transmit pins that

support up to 32 transmit or 32 receive channels of audio data

when all eight SPORTs are enabled, or eight duplex TDM

streams of 128 channels per frame.

For the ADSP-21375, serial ports are enabled via eight program-

mable pins and simultaneous receive or transmit pins that

support up to 16 transmit or 16 receive channels of audio data

when all four SPORTs are enabled, or four duplex TDM streams

of 128 channels per frame.

The serial ports operate at a maximum data rate of f PCLK /4.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

Rev. D | Page 8 of 56 | April 2013

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